Formal Design Verification Engineer- 93761 (m/w/d)

Arbeitsort: 80539 München


What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.Title : Formal Verification EngineerThe Role : This position is for a design verification engineer. The successful candidate will use formal verification technologies to complete functional verification of state-of-art design. Formal technologies include Formal Property Verification (FPV), Sequential Equivalence Check (SEC/SEQ/SLEC), Connectivity Check (CC).The Person : Will enjoy learning, growing and working in a fast paced environmentResponsiblities :Crafting verification planWriting formal propertiesRunning formal verification toolsDebugging failuresDiscussing issues with designersDocument, report and issue trackingPreferred skillset & Experience:A property language like SystemVerilog Assertion (SVA)Understanding a HDL language like Verilog or VHDLConcept and flow of design verificationPrevious FPV experience or eager to learnEducation : Electrical or Computer EngineeringLocation : Ontario or Alberta*LI-AP1Requisition Number: 93761
Country/Region/Location: Germany State/Province: Bavaria City: Munich
Job Function: Design


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